1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor device using a clock and a semiconductor system including the semiconductor device.
2. Description of the Related Art
A semiconductor device operates at a predetermined rate in a semiconductor system. The semiconductor device is in need of a clock to operate at the predetermined rate. The clock is generated from a control device in the semiconductor system and it pulses at a predetermined frequency.
Differential clocks having two signals that are opposite in phase will be discussed herein. Since the differential clocks are characteristically resistant to noise when recognized or amplified, they may support a secure semiconductor system with operational reliability.
FIG. 1 is a block view of a typical semiconductor system. Referring to FIG. 1, the semiconductor system includes a control device 10, first and second semiconductor devices 20 and 30, and a substrate 40. The control device 10 generates differential clocks WCK and WCKB, an address ADD, and various commands CMD. The first and second semiconductor devices 20 and 30 perform predetermined operations in response to the differential clocks WCK and WCKB, the address ADD, and the various commands CMD. The substrate 40 includes a routing path for transferring the differential clocks WCK and WCKB, the address ADD, and the various commands CMD.
Herein, the control device 10 includes a processor such as a Graphic Processing Unit (GPU).
The first and second semiconductor devices 20 and 30 include a memory device, such as a Dynamic Random Access Memory (DRAM) device. The first semiconductor device 20 is mounted on one side of the substrate 40, while the second semiconductor device 30 is mounted on the other side of the substrate 40 (the devices are mounted facing each other in a mirrored structure). The first semiconductor device 20 will be referred to as the main semiconductor device, and the second semiconductor device 30 is referred to as the mirrored semiconductor device.
The main semiconductor device 20 and the mirrored semiconductor device 30 have a mirrored structure relative to each other making the array of pads opposite to each other. The same signal is inputted to the pads of both semiconductor devices 20 and 30 through the routing path of the substrate 40. Both the main semiconductor device 20 and the mirrored semiconductor device 30 each have positive and negative clock pads. The positive clock WCK of the differential clocks WCK and WCKB is inputted to the positive clock pad of the main semiconductor device 20 and the negative clock pad of the mirrored semiconductor device 30. A negative clock WCKB of the differential clocks WCK and WCKB is inputted to the negative clock pad of the main semiconductor device 20 and the positive clock pad of the mirrored semiconductor device 30.
A signal may be inputted to the main semiconductor device 20 through a designated pad and not inputted to the mirrored semiconductor device 30. A signal representing which semiconductor device is mirrored, called the mirror function signal, is therefore required.
The mirror function signal MF is disabled in the main semiconductor device 20 (MF=0) while the mirror function signal MF is enabled in the mirrored semiconductor device 30 (MF=1). The main semiconductor device 20 uses the signals inputted through the corresponding pads in response to the disabled mirror function signal MF, whereas the mirrored semiconductor device 30 uses the signals inputted through the corresponding pads by internally reallocating them in response to the enabled mirror function signal MF.
FIG. 2 is a block view illustrating an internal structure of the main semiconductor device 20 shown in FIG. 1. Referring to FIG. 2, the main semiconductor device 20 includes a buffer unit 21, a differential clock recognition unit 23, a pre-output unit 25, and a main output unit 27. The buffer unit 21 generates a mirror function enable signal ENMF by buffering a mirror function signal MF inputted through a mirror function pad PD00. The differential clock recognition unit 23 recognizes a positive clock WCK inputted through a positive clock pad PD01 as an internal positive clock WCKOUT and recognizes a negative clock WCKB inputted through a negative clock pad PD02 as an internal negative clock WCKOUTB in response to the mirror function enable signal ENMF and an operation enable signal BUFEN. The pre-output unit 25 serializes first to eighth internal parallel data RGIO_EV0 to RGIO_OD3 in pairs and outputs first to fourth pre-parallel data D04D to D37B. The main output unit 27 serially outputs the first to fourth pre-parallel data D04D to D37B through a data pad PD03 in response to the internal differential clocks WCKOUT and WCKOUTB.
Herein, the mirror function signal MF includes a signal that is fixed at a predetermined voltage level. For example, the mirror function pad PD00 is coupled with a ground voltage terminal (not shown in the drawing), and thus the mirror function signal MF is disabled to a logic low level (MF=0).
Meanwhile, the differential clock recognition unit 23 recognizes that the predetermined positive clock WCK and negative clock WCKB are inputted through the positive clock pad PD01 and the negative clock pad PD02 based on the disabled mirror function enable signal ENMF, and outputs the positive clock WCK and the negative clock WCKB as an internal positive clock WCKOUT and an internal negative clock WCKOUTB.
FIG. 3 is a block view illustrating an internal structure of the mirrored semiconductor device 30 shown in FIG. 1. Referring to FIG. 3, the mirrored semiconductor device 30 includes a buffer unit 31, a differential clock recognition unit 33, a pre-output unit 35, and a main output unit 37. The buffer unit 31 generates a mirror function enable signal ENMF by buffering a mirror function signal MF inputted through a mirror function pad PD10. The differential clock recognition unit 33 recognizes a negative clock WCKB inputted through a positive clock pad PD11 as an internal negative clock WCKOUTB and recognizes a positive clock WCK inputted through a negative clock pad PD12 as an internal positive clock WCKOUT in response to the mirror function enable signal ENMF and an operation enable signal BUFEN. The pre-output unit 35 serializes first to eighth internal parallel data RGIO_EV0 to RGIO_OD3 in pairs and outputs first to fourth pre-parallel data D04D to D37B. The main output unit 37 serially outputs the first to fourth pre-parallel data D04D to D37B through a data pad PD13 in response to the internal differential clocks WCKOUT and WCKOUTB.
Herein, the mirror function signal MF includes a signal that is fixed at a predetermined voltage level. For example, the mirror function pad PD10 is coupled with a power supply voltage terminal (not shown in the drawing), and thus the mirror function signal MF is enabled to a logic high level (MF=1).
The differential clock recognition unit 33 recognizes that the negative clock WCKB and the positive clock WCK, which should not be inputted, are inputted through the positive clock pad PD11 and the negative clock pad PD12 based on the enabled mirror function enable signal ENMF, reallocates the positive clock WCK and the negative clock WCKB, and outputs an internal positive clock WCKOUT and an internal negative clock WCKOUTB.
Described hereafter is an operation of the semiconductor system having the above-described structure with reference to FIG. 4.
FIG. 4 is a timing diagram describing the operation of the semiconductor system illustrated in FIG. 1. Referring to FIG. 4, the main semiconductor device 20 and the mirrored semiconductor device 30 perform a data read operation under the control of the control device 10. For example, the main semiconductor device 20 and the mirrored semiconductor device 30 perform a read operation in response to differential clocks WCK and WCKB, a read command CMD, and row and column addresses ADD.
First, the operation of the main semiconductor device 20 is described. Referring to. FIG. 2, the differential clock recognition unit 23 recognizes and outputs a clock WCK inputted through the positive clock pad PD01 as an internal positive clock WCKOUT and recognizes and outputs a clock WCKB inputted through the negative clock pad PD02 as an internal negative clock WCKOUTB in response to a disabled mirror function enable signal ENMF.
In this state, the pre-output unit 25 serializes the first to eighth internal parallel data RGIO_EV0 to RGIO_OD3 that are read through a read operation in pairs and outputs first to fourth pre-parallel data D04D to D37B. The main output unit 27 serially outputs the first to fourth pre-parallel data D04D to D37B through the data pad PD03 in response to the internal differential clocks WCKOUT and WCKOUTB. The main output unit 27 generates first to fourth divided clocks ICLK to QCLKB by dividing the internal differential clocks WCKOUT and WCKOUTB, and serially outputs the first to fourth pre-parallel data D04D to D37B through the data pad PD03 in response to the first to fourth divided clocks ICLK to QCLKB.
Subsequently, the operation of the mirrored semiconductor device 30 is described. The differential clock recognition unit 33 recognizes and outputs a clock WCKB inputted through the positive clock pad PD11 as an internal negative clock WCKOUTB and recognizes and outputs a clock WCK inputted through the negative clock pad PD12 as an internal positive clock WCKOUT in response to an enabled mirror function enable signal ENMF.
In this state, the pre-output unit 35 serializes the first to eighth internal parallel data RGIO_EV0 to RGIO_OD3 that are read through a read operation in pairs and outputs first to fourth pre-parallel data D04D to D37B. The main output unit 37 serially outputs the first to fourth pre-parallel data D04D to D37B through the data pad PD13 in response to the internal differential clocks WCKOUT and WCKOUTB. The main output unit 37 generates first to fourth divided clocks ICLK to QCLKB by dividing the internal differential clocks WCKOUT and WCKOUTB, and serially outputs the first to fourth pre-parallel data D04D to D37B through the data pad PD13 in response to the first to fourth divided clocks ICLK to QCLKB.
According to the read operation described above, the main semiconductor device 20 and the mirrored semiconductor device 30 output read data MXOUT0 and MXOUT1 to the control device 10 at the same time theoretically. To be specific, the main semiconductor device 20 and the mirrored semiconductor device 30 output the read data MXOUT0 and MXOUT1 through the data pads PD03 and PD13 after a Column Address Strobe (CAS) latency CL passes from a moment when the read command CMD is inputted. Therefore, the control device 10 judges the read data MXOUT0 and MXOUT1 at a predetermined judge point.
The main semiconductor device 20 and the mirrored semiconductor device 30 may have different skew reflected into the read data MXOUT0 and MXOUT1 due to a mismatch that is different for each device. For example, if there is a mismatch between a layout of a transfer line through which the positive clock WCK is transferred and a layout of a transfer lime through which the negative clock WCKB is transferred, the read data MXOUT0 outputted from the main semiconductor device 20 and the read data MXOUT1 outputted from the mirrored semiconductor device 30 may have different skew.
As illustrated in FIG. 4, the read data MXOUT0 outputted from the main semiconductor device 20 has skew from a data eye pattern to the left side, whereas the read data MXOUT1 outputted from the mirrored semiconductor device 30 has skew from the data eye to the right side. In this case, the valid window that is in common between the read data MXOUT0 and MXOUT1 becomes so small that the control device 10 suffers a failure occurring when it judges the read data MXOUT0 and MXOUT1 at a predetermined judge point.